asahi kasei [AKD4121A] 2007/03 - 1 - general description the AKD4121A is the evaluation board for the ak4121a, 96khz asynchronous sample rate converter. this board has the optical connectors to interface with other digital audio equipments and serial interfaces for akm ad/da evaluation boards. the AKD4121A achieves quick evaluation of ak4121a ? ordering guide AKD4121A --- evaluation board for ak4121a function ? optical fiber connectors (for digital audio interface. input x 1, output x 1.) ? 10pin header (for akm ad/da evaluation board. input x 1, output x 1.) ? on board x?tal oscillator (input x 1, output x 1.) 10pin header (ak4112b) dir ak4121a (ak4114) clock generator 3 jp1 imclk jp2 4 pdn sw1 smute sw2 3 3 imclk ibick ilrck sdti 3 dir jp6 dit-source jp11 3 bypass src-mclk jp5 port3 port1 omclk obick sdto olrck d5v +3.3v +3.3v d5v d5v +3.3v dit optical input port2 ~ +3.3v d5v t1 48m003f out gnd in 5v or 3.3v 3 optical output port4 sw3 fsi-dir sw4 cmode sw5 fso 2 3 2 3 jp7~9 10pin header in out port3 port3 dit jp10 3.3v reg jack figure 1. AKD4121A block diagram *circuit diagram and pcb layout are a ttached at the end of this manual. ak4121a evaluation board rev.0 a kd4121 a
asahi kasei [AKD4121A] 2007/03 - 2 - evaluation board manual contents ? operating sequence --------------------------------------------------------------------------------------- p. 3 1. jumper setting for power supply: jp10(reg) 2. power supply line setting 3. dip switch and jumper pin setting 4. power-on ? dip switch and jumper pin setting ------------------------------------------------------------------ p. 4 1. setting of fsi (input fs) block -------------------------------------------------------------------------- p. 4 1-1. in case of using optical input. 1-2. all clock are fed through the 10-pin port. 1-3. sdti is fed through the 10-pin port and others are fed from the dir(ak4112b). 2. setting of fso (output fs) block ---------------------------------------------------------------------- p. 9 2-1. in case of providing clock from dit. 2-2. in case of providing clock from 10pin port 2-2-1. ak4121a master mode. 2-2-2. ak4121a slave mode. 3. bypass mode --------------------------------------------------------------------------------------------------- p.22 4. setting of the others -------------------------------------------------------------------------------------- p.22 4-1. de-emphasis filter. 4-2. soft mute. ? jumper list --------------------------------------------------------------------------------------------------- p.21 ? dip switch list --------------------------------------------------------------------------------------------------- p.21 ? toggle switch list --------------------------------------------------------------------------------------------- p.22 ? led ---------------------------------------------------------------------------------------------------------------- p.22 ? measurement results --------------------------------------------------------------------------------------- p.23 ? important notice --------------------------------------------------------------------------------------------- p.29 ? circuit diagram ? pcb layout
asahi kasei [AKD4121A] 2007/03 - 3 - ? operating sequence please use the AKD4121A according to the following sequence. 1. jumper setting for power supply: jp10(3.3v) the jp10 (3.3v) selects power supply of the AKD4121A.(3.3v or 5v.) jack : providing power supply voltage with 3.3v. opticlal input is not avaible. reg : providing power supply voltage with 5v. (3.3v is supplied via regulator on board.) 2. power supply line setting each supply line should be distributed directly from the power supply unit with low impedance connection. 5v or 3.3v : for power supply jack. 5v or 3. 3v. (power supply voltage is selectrd by jp10.) gnd : groung of the board. 0v. 3. dip switch and jumper pins setting (refer next page) 4. power-on (after power is on, sw1 shoul d be reset by setting "l" "h" once.) * the reset is done by sw1 during opertion. the ak4121a is powered down during sw1 is ?l?. the power down state is canceld by briging the sw1 to ?h?, at the same time, the ak4121a is reset.
asahi kasei [AKD4121A] 2007/03 - 4 - ? dip switch and jumper pin setting 1. setting of fsi (input fs) block 1-1. optical input (port2) 1-1-a. jumper setting parts no. setting jp1 (don?t care) jp2 short jp3 short jp4 short sw3-4 off x1 (don?t care) table 1. jumper setting (refer following figures) jp4 ilrck jp1 imclk jp3 sdti jp2 ibick out in figure 2. jumper setting 1-1-b. audio interface format setting(iis only) 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk figure 3. dip switch (sw3) setting
asahi kasei [AKD4121A] 2007/03 - 5 - 1-2. all clock are fed through the 10-pin port 1-2-a. jumper setting parts no. setting jp1 (don?t care) jp2 open jp3 open jp4 open sw3-4 (don?t care) x1 (don?t care) table 2. jumper setting (refer following figures) jp4 ilrck jp1 imclk jp3 sdti jp2 ibick out in figure 4. jumper setting 1-2-b. audio interface format setting src:ak4121a sw3-1 sw3-2 sw3-3 audio interface format dif2 dif1 dif0 16bit, right justified 0 0 0 20bit, right justified 0 0 1 left justified 0 1 0 i 2 s 0 1 1 24bit, right justified 1 0 0 table 3. dip switch (sw3) setting(refer following figures) 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk 16bit, right justified 20bit, right justified
asahi kasei [AKD4121A] 2007/03 - 6 - 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk left justified i 2 s 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk 24bit, right justified figure 5. dip switch setting
asahi kasei [AKD4121A] 2007/03 - 7 - 1-3. sdti is fed through the 10-pin port and other clocks are fed from the ak4112b. the x1(x?tal) or external clock (via port1) can be us ed as the system clock of the input block. please remove x1 when unsed. the system cloc k can be selected as 256fsi or 512fs i. this clock is not used for the ak4121a directly. 1-3-a. jumper setting parts no. setting jp1 open: using x?tal in : system clock providing from 10port jp2 short jp3 open jp4 short table 4. dip switch (sw3) setting(refer following figures) jp4 ilrck jp1 imclk jp3 sdti jp2 ibick out in using x?tal setting jp4 ilrck jp1 imclk jp3 sdti jp2 ibick out in using external clock figure 6. jumper setting
asahi kasei [AKD4121A] 2007/03 - 8 - dip sw3 setting no. x?tal / external clock (max: 24.576mhz) dir-cm0 sw3-4 ocks0 sw3-5 1 256fs on 1/2 mclk 2 512fs on mclk table 5. dir(ak4112b)?s clock setting(refer following figures) 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk mclk:256fsi mclk:512fsi figure 7. dip sw(sw3) setting(refer following figures) 1-3-b audio interface format setting refer ?1-2-b refer audio interface format setting?
asahi kasei [AKD4121A] 2007/03 - 9 - 2. setting of fso (output fs) block 2-1. optical output(port4). clocks are fed fr om ak4114 (dit). (iis master mode only.) the x2(x?tal) or external clock via port3 can be used as the system clock of the output block. please remove x2 when unused. 2-1-a. jumper setting parts no. setting jp5 dit jp6 open: using x?tal on board port3: clock input form port3 (dir: using clock from dir for bypass mode) jp7 short jp8 short jp9 short jp11 open table 6. jumper setting (refer following figures) jp7 ilrck jp5 src-mclk jp9 olrck jp8 obick dit port3 using on-board x?tal jp11 10pin bypass output jp6 dit-source port3 dir jp7 ilrck jp5 src-mclk jp9 olrck jp8 obick dit port3 using external clock jp11 10pin bypass output jp6 dit-source port3 dir figure 8. jumper setting
asahi kasei [AKD4121A] 2007/03 - 10 - 2-1-b. dip sw setting x2 or external clock sw4-1 sw4-2 sw4-3 sw5-3 cmode2 cmode1 cmode0 ocks0 256fs l l l 1/2 mclk 512fs l h l mclk table 7. clock setting(refer following figures) 12345 cmode2 cmode1 cmode0 sw4 cmode dem0 dem1 123 mclk sw5 fso odif1 odif0 1/2 mclk 12345 cmode2 cmode1 cmode0 sw4 cmode dem0 dem1 123 mclk sw5 fso odif1 odif0 1/2 mclk 256fso 512fso figure 9. dip switch setting
asahi kasei [AKD4121A] 2007/03 - 11 - 2-2. clocks are fed through the 10-pin port(port3) 2-2-1. ak4121a in master mode 2-2-1-a. jumper setting table 8. jumper setting(refer following figures) jp7 sdto jp5 src-mclk jp9 olrck jp8 obick dit port3 using x?tal on-board jp11 10pin bypass output jp6 dit-source port3 dir figure 10. jumper setting 2-2-1-b. audio interface format mod e sw4-1 cmode2 sw4-2 cmode1 sw4-3 cmode0 mclk master/slave (output port) 0 l l l 256fso (fso~96khz) master 1 l l h 384fso (fso~96khz) master 2 l h l 512fso (fso~48khz) master 3 l h h 768fso (fso~48khz) master table 9. ak4121a system clock setting parts no. setting jp5 port3 jp6 open jp8 open jp9 open jp7 open jp11 open
asahi kasei [AKD4121A] 2007/03 - 12 - mode sw5-1 odif1 sw5-2 odif0 sdto format obick (slave) obick (master) 0 l l 16bit lsb justified 64fs 64fs 1 l h 20bit lsb justified 64fs 64fs 2 h l 20bit msb justified 40fs 64fs 3 h h 20bit i 2 s compatible 40fs or 32fs 64fs table 10. ak4121a audio interface format setting 123 mclk sw5 fso odif1 odif0 1/2 mclk 123 mclk sw5 fso odif1 odif0 1/2 mclk 16bit, right justified 20bit, right justified 123 mclk sw5 fso odif1 odif0 1/2 mclk 123 mclk sw5 fso odif1 odif0 1/2 mclk left justified i 2 s figure 11. dip switch setting
asahi kasei [AKD4121A] 2007/03 - 13 - 2-2-2. ak4121a in slave mode 2-2-2-a. jumper setting parts no. setting jp5 port3 jp6 open jp8 open jp9 open jp7 open jp11 open table 11. jumper setting(refer following figures) jp7 sdto jp5 src-mclk jp9 olrck jp8 obick dit port3 using external clock jp11 10pin bypass output jp6 dit-source port3 dir figure 12. jumper setting 2-2-2-b. audio interface format mod e sw4-1 cmode2 sw4-2 cmode1 sw4-3 cmode0 mclk master/slave (output port) 4 h l l not used. set to dvss slave table 12. ak4121a system clock setting 12345 cmode2 cmode1 cmode0 sw4 cmode dem0 dem1 figure 13. dip switch setting
asahi kasei [AKD4121A] 2007/03 - 14 - mode sw5-1 odif1 sw5-2 odif0 sdto format obick (slave) obick (master) 0 l l 16bit lsb justified 64fs 64fs 1 l h 20bit lsb justified 64fs 64fs 2 h l 20bit msb justified 40fs 64fs 3 h h 20bit i 2 s compatible 40fs or 32fs 64fs table 13. ak4121a audio interface format setting 123 mclk sw5 fso odif1 odif0 1/2 mclk 123 mclk sw5 fso odif1 odif0 1/2 mclk 16bit, right justified 20bit, right justified 123 mclk sw5 fso odif1 odif0 1/2 mclk 123 mclk sw5 fso odif1 odif0 1/2 mclk left justified i 2 s figure 14. dip switch setting
asahi kasei [AKD4121A] 2007/03 - 15 - 3. bypass mode in case of bypass mode, please set dip switch (sw3) as follows. mod e sw4-1 cmode2 sw4-2 cmode1 sw4-3 cmode0 mclk master/slave (output port) 7 h h h not used. set to dvss master(bypass) table 14. ak4121a system clock setting 12345 cmode2 cmode1 cmode0 sw4 cmode dem0 dem1 figure 13. dip switch setting 3-1. setting of input block 3-1-1. optical input(port2) 3-1-1-a. jumper setting parts no. setting jp1 out jp2 short jp3 short jp4 short x1 (don?t care) table 15. jumper setting(refer following figures) jp4 ilrck jp1 imclk jp3 sdti jp2 ibick out in figure 14. jumper setting 3-1-1-b. audio interface format setting (iis only) 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk figure 15. dip switch (sw3) setting
asahi kasei [AKD4121A] 2007/03 - 16 - 3-1-2. all clock are fed through the 10-pin port 3-1-2-a. jumper setting parts no. setting jp1 out jp2 open jp3 open jp4 open x1 (don?t care) table 16. jumper setting(refer following figures) jp4 ilrck jp1 imclk jp3 sdti jp2 ibick out in figure 16. jumper setting 3-1-2-b. audio interface format src:ak4121a sw3-1 sw3-2 sw3-3 audio interface format dif2 dif1 dif0 16bit, right justified 0 0 0 20bit, right justified 0 0 1 left justified 0 1 0 i 2 s 0 1 1 24bit, right justified 1 0 0 table 17. dip switch (sw3) setting 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk 16bit, right justified 20bit, right justified
asahi kasei [AKD4121A] 2007/03 - 17 - 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk left justified i 2 s 12345 idif2 idif1 idif0 sw3 fsi-dir dir-cm0 1/2mclk mclk 24bit, right justified figure 17. dip switch (sw3) setting
asahi kasei [AKD4121A] 2007/03 - 18 - 3-2. setting of output block 3-2-1. optical output(port4). clock are fed from ak4114 (dit). (iis master mode only.) 3-2-1-a. jumper setting parts no. setting jp8 short jp9 short jp7 short jp5 (don?t care) jp6 dir jp11 open x2 remove table 18. jumper setting jp7 ilrck jp5 src-mclk (don?t care) jp9 olrck jp8 obick dit port3 jp11 10pin bypass output jp6 dit-source port3 dir figure 18. jumper setting dip sw3 setting dip sw5 setting no. x1or external clock (port1) (max: 24.576mhz) ocks0 sw3-5 ocks0 sw5-3 1 256fs 1/2 mclk 1/2 mclk 2 512fs mclk mclk table 19. dir/di t clock setting 123 mclk sw5 fso odif1 odif0 1/2 mclk 123 mclk sw5 fso odif1 odif0 1/2 mclk mclk:256fso mclk:512fso figure 19. dip switch setting
asahi kasei [AKD4121A] 2007/03 - 19 - 3-2-2. clock are fed through the 10-pin port(port3) 3-2-2-a. jumper setting parts no. setting jp8 open jp9 open jp7 open jp5 (don?t care) jp6 open jp11 open x2 (don?t care) table20. jumper setting jp7 ilrck jp5 src-mclk (don?t care) jp9 olrck jp8 obick dit port3 jp11 10pin bypass output jp6 dit-source port3 dir figure 20. jumper setting 3-2-2-b. audio interface format mode sw5-1 odif1 sw5-2 odif0 sdto format obick (master) 0 l l 16bit lsb justified 64fs 1 l h 20bit lsb justified 64fs 2 h l 20bit msb justified 64fs 3 h h 20bit i 2 s compatible 64fs table 21. ak4121a audio interface format setting 123 mclk sw5 fso odif1 odif0 1/2 mclk 123 mclk sw5 fso odif1 odif0 1/2 mclk 16bit, right justified 20bit, right justified 123 mclk sw5 fso odif1 odif0 1/2 mclk 123 mclk sw5 fso odif1 odif0 1/2 mclk left justified i 2 s figure 21. dip switch setting
asahi kasei [AKD4121A] 2007/03 - 20 - 4. the other setting 4-1. de-emphasis filter sw4-4 and sw4-5 control the de-emphasis filter. mode sw4-4 dem1 sw4-5 dem0 de-emphasis filter 0 l l 44.1khz 1 l h off 2 h l 48khz 3 h h 32khz table22. de-emphasis filter setting 4-2. soft mute toggle switch sw2 controls the soft mute. mode sw2 smute soft mute 0 off off 1 on on table23. soft mute setting
asahi kasei [AKD4121A] 2007/03 - 21 - ? jumper list no. jumper name default function 10 3.3v reg power supply select for AKD4121A reg : power supply for AKD4121A is 5v. the vdd(3.3v) of ak4121a is supplied from the regulator. jack : power supply for AKD4121A is 3.3v. optical link is not available. 1 imclk in mclk select for fsi port. in on-board x?tal(x1). out : external clock. 2, 3, 4 ibick, ilrck, sdti short input select for fsi port. open : port2 clock. short : dir clock. 5 src-mclk dit mclk select for fso port. dit : dit (ak4114) clock. port3 : external clock. 6 dit-soruce open dit-soruce select. open on-board x?tal(x2). dir : dir(ak4112b) clock. port3: port3 clock. 11 10 pin bypass output open bypass mode select. short : setting for bypass mode. open : for other modes. 7, 8, 9 obick, olrck, sdto short output select for fso port. open : use only port3. not use dit (ak4114) clock. short : use dit clock.
asahi kasei [AKD4121A] 2007/03 - 22 - ? dip switch list sw3(fsi-dir) no. switch name default function 1, 2, 3 idif2, 1, 0 off, on, on (iis) fsi data format. refer table 3. 4 dir-cm0 off (optical) dir clock mode. on : x?tal mode off : optical mode 5 mclk 1/2mclk mclk dir mclk select. mclk : 512fs 1/2mclk : 256fs sw4(cmode) no. switch name default function 1, 2, 3 cmode2, 1, 0 off, on, off (master, 512fso) system clock selects. refer table 9, table 12 and table 14 4, 5 dem1, 0 off, on (off) de-e mphasis control. refer table 12. sw5(fso) no. switch name default function 1,2 odif1, 0 on, on (iis) fso data format. refer table 10. 3 mclk 1/2mclk mclk dit mclk select. mclk : 512fs 1/2mclk : 256fs ? toggle switch list (sw1 and sw2) sw1 is reset switch for ak4121a, ak4112b(dir) and ak4114(dit). set to ?h? during normal operation. bring to ?l? once after the power is supplied. sw2 is smute control switch. refer table 23. ? led bright when erf pin of ak4112b goes to ?h?. this indicates the unlock state, etc. (refer ak4112b datasheet).
asahi kasei [AKD4121A] 2007/03 - 23 - measurement results [measurement conditions] measurement unit : audio precision system two cascade vdd : 3.3v tvdd : 5v input data : 44.1khz, 20bit, i 2 s output data : 48khz; 20bit, i 2 s interface : optical fiber parameter input signal measurement filter results thd+n 1khz, 0db fs/2 ? 113.5 db dr 1khz, -60db fs/2 115.2 db dr 1khz, -60db fs/2, a-weighted 117.6 db
asahi kasei [AKD4121A] 2007/03 - 24 - a km ak4121 src fft (fsi=44.1khz, fso=48khz; fin=1khz, 0dbfs input) fft points 16384, avg.=8, window=equiripple -180 +0 -160 -140 -120 -100 -80 -60 -40 -20 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz a km ak4121 src fft (fsi=44.1khz, fso=48khz; fsi=1khz, -60dbfs input) fft points 16384, avg.=8, window=equiripple -180 +0 -160 -140 -120 -100 -80 -60 -40 -20 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz ak4121a ak4121a
asahi kasei [AKD4121A] 2007/03 - 25 - a km ak4121 src thd+n vs. input frequenc y ( fsi=44.1khz, fso=48khz; 0dbfs input ) -130 -90 -127.5 -125 -122.5 -120 -117.5 -115 -112.5 -110 -107.5 -105 -102.5 -100 -97.5 -95 -92.5 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz a km ak4121 src thd+n vs. input frequency (fsi=44.1khz, fso=48khz; -60dbfs input) -130 -90 -127.5 -125 -122.5 -120 -117.5 -115 -112.5 -110 -107.5 -105 -102.5 -100 -97.5 -95 -92.5 d b f s 20 20k 50 100 200 500 1k 2k 5k 10k hz ak4121a ak4121 a
asahi kasei [AKD4121A] 2007/03 - 26 - a km a k4121 src thd+n vs. input level (fsi=44.1khz, fso=48khz; fin=1khz) -130 -100 -128 -126 -124 -122 -120 -118 -116 -114 -112 -110 -108 -106 -104 -102 d b f s -130 +0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs a km a k4121 src linearity (fsi=44.1khz, fso=48khz; fin=1khz) -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d b f s -140 +0 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs ak4121 a ak4121a
asahi kasei [AKD4121A] 2007/03 - 27 - akm ak4121 src frequency response (fsi=44.1khz, fso=48khz, 0dbfs input) -0.25 -0.15 -0.24 -0.23 -0.22 -0.21 -0.2 -0.19 -0.18 -0.17 -0.16 d b f s 2k 24k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k hz ak4121 frequency response (blue:fsi=48khz, red:fsi=96khz) vdd=3.3v, tvdd=5.0v, fso=48khz -14 -0 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 d b f s 2k 22k 4k 6k 8k 10k 12k 14k 16k 18k 20k hz fsi=96khz fsi=48khz ak4121a ak4121a
asahi kasei [AKD4121A] 2007/03 - 28 - akm ak4121 frequency response (blue:fsi=44.1khz, red:fsi=48khz, gray:fsi=96khz) vdd=3.3v, tvdd=5.0v, fso=44.1khz -22 -0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 d b f s 2k 22k 4k 6k 8k 10k 12k 14k 16k 18k 20k hz ak4121a fsi=96khz fsi=48khz fsi=44.1khz
asahi kasei [AKD4121A] 2007/03 - 29 - revision history date (yy/mm/dd) manual revision board revision reason contents 07/03/22 km088800 0 first edition important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems co ntaining them, may require an export license or other official approval under the law and regulations of th e country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the repres entative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of li fe or in significant injury or damage to person or property. (b) a critical component is one whos e failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very hi gh standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes , disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all resp onsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
5 5 4 4 3 3 2 2 1 1 d d c c b b a a 5v or 3.3v ibick sdti ilrck ilrck d5v pdn sdti dir-ocks1 ibick d5v d5v +3v +3v dir-cm0 d5v mclk12 +3v d5v d5v d5v title size document number rev date: sheet of ak4112b 0 AKD4121A a3 13 tuesday, march 20, 2007 title size document number rev date: sheet of ak4112b 0 AKD4121A a3 13 tuesday, march 20, 2007 title size document number rev date: sheet of ak4112b 0 AKD4121A a3 13 tuesday, march 20, 2007 h l out in lrck12 bck12 sdto12 ilrck imclk ibick sdti ibick sdti ilrck jack reg + c2 10u + c2 10u c8 0.1u c8 0.1u r1 10k r1 10k + c12 10u + c12 10u r4 18k r4 18k r29 220k r29 220k + c30 47u + c30 47u 1 2 u5a 74hc14 u5a 74hc14 led1 erf led1 erf r21 100 r21 100 l2 47u l2 47u c6 open c6 open r30 220k r30 220k c29 0.1u c29 0.1u 1 2 3 jp10 3.3v jp10 3.3v r6 1k r6 1k c10 0.1u c10 0.1u dvdd 1 dvss 2 tvdd 3 v/tx 4 xti 5 xto 6 pdn 7 r 8 avdd 9 avss 10 rx1 11 rx2/dif0 12 rx3/dif1 13 rx4/dif2 14 auto 15 p/s 16 fs96 17 erf 18 lrck 19 sdto 20 bick 21 daux 22 mcko2 23 mcko1 24 ocks0/csn 25 ocks1/cclk 26 cm1/cdti 27 cm0/cdto 28 u1 ak4112b u1 ak4112b c11 0.1u c11 0.1u c7 open c7 open c32 0.1u c32 0.1u r2 short r2 short r31 220k r31 220k 2 1 d1 hsu119 d1 hsu119 r22 100 r22 100 c3 0.1u c3 0.1u 1 2 3 jp1 imclk jp1 imclk x1 22.5792mhz x1 22.5792mhz + c31 47u + c31 47u + c9 10u + c9 10u out 1 vcc 3 gnd 4 gnd 2 6 6 5 5 port2 dir1 port2 dir1 jp3 jp3 l1 10u l1 10u 3 4 u5b 74hc14 u5b 74hc14 1 2 3 4 5 6 7 8 9 10 port1 port1 2 1 3 sw1 pdn sw1 pdn r23 100 r23 100 c5 0.1u c5 0.1u 5 6 u5c 74hc14 u5c 74hc14 out 1 gnd 3 in 2 t1 ta48m033f t1 ta48m033f c1 0.1u c1 0.1u r5 470 r5 470 jp4 jp4 jp2 jp2 r3 10k r3 10k + c4 10u + c4 10u r24 100 r24 100
5 5 4 4 3 3 2 2 1 1 d d c c b b a a sdto omclk olrck xti xto dit-mclk d5v +3v omclk obick dit-mclk +3v obick olrck +3v sdto dit-ocks1 mclk12 src-mclk xti pdn xto d5v d5v d5v d5v title size document number rev date: sheet of ak4114 0 AKD4121A a3 23 tuesday, march 20, 2007 title size document number rev date: sheet of ak4114 0 AKD4121A a3 23 tuesday, march 20, 2007 title size document number rev date: sheet of ak4114 0 AKD4121A a3 23 tuesday, march 20, 2007 sdto obick olrck dit dir 10pin-port3 lrck14 port3 dit bck14 sdti14 dir port3 (open x'tal) opt 10pin bypass output sdto obick olrck r26 100 r26 100 1 2 3 4 5 6 7 8 9 10 port3 port3 + c13 10u + c13 10u c19 0.1u c19 0.1u r10 1k r10 1k c17 open c17 open jp7 jp7 + c22 10u + c22 10u c14 0.1u c14 0.1u jp9 jp9 r9 18k r9 18k c20 0.1u c20 0.1u r27 100 r27 100 jp11 jp11 + c16 0.47u + c16 0.47u r25 100 r25 100 r7 short r7 short ips0/rx4 1 avss 2 dif0/rx5 3 test2 4 dif1/rx6 5 avss 6 dif2/rx7 7 ips1/iic 8 p/sn 9 xtl0 10 xtl1 11 vin 12 tvdd 13 dvss 14 tx0 15 tx1 16 bout 17 cout 18 uout 19 vout 20 dvdd 21 dvss 22 mcko1 23 lrck 24 sdto 25 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0/cdto 32 cm1/cdti 33 ocks1/cclk 34 ocks0/csn 35 int0 36 int1 37 avdd 38 r 39 vcom 40 avss 41 rx0 42 avss 43 rx1 44 test1 45 rx2 46 avss 47 rx3 48 u3 ak4114 u3 ak4114 r8 10k r8 10k r28 100 r28 100 c21 0.1u c21 0.1u 1 2 3 jp6 dit-source jp6 dit-source r34 220k r34 220k 1 2 x2 24.576 mhz x2 24.576 mhz 1 2 3 jp5 src-mclk jp5 src-mclk r32 220k r32 220k c15 open c15 open + c18 10u + c18 10u gnd 1 if 2 vcc 3 in 4 5 5 6 6 port4 totx176 port4 totx176 jp8 jp8 r33 220k r33 220k
5 5 4 4 3 3 2 2 1 1 d d c c b b a a d5v sdto olrck src-mclk obick pdn d5v cmode1 cmode0 odif0 odif1 idif0 idif1 cmode2 idif2 +3v dit-ocks1 sdti ibick ilrck dem1 dem0 odif1 odif0 d5v dem1 dem0 cmode2 cmode1 cmode0 idif2 idif1 idif0 dir-cm0 dir-ocks1 title size document number rev date: sheet of ak4121a 0 AKD4121A a3 33 thursday, march 22, 2007 title size document number rev date: sheet of ak4121a 0 AKD4121A a3 33 thursday, march 22, 2007 title size document number rev date: sheet of ak4121a 0 AKD4121A a3 33 thursday, march 22, 2007 odif0 odif1 cmode2 1/2mclk mclk idif2 idif1 idif0 dir-cm0 mclk 1/2mclk off on dem1 dem0 cmode1 cmode0 r44 47k r44 47k 1 2 3 6 5 4 sw5 fso sw5 fso 1 2 3 4 5 10 9 8 7 6 sw4 cmode sw4 cmode r36 47k r36 47k r39 47k r39 47k r35 47k r35 47k c24 0.1u c24 0.1u r11 560 r11 560 r37 47k r37 47k r41 47k r41 47k r47 47k r47 47k 9 8 u2d 74hc14 u2d 74hc14 r40 47k r40 47k r43 47k r43 47k r45 47k r45 47k c26 1.0n c26 1.0n c25 4.7u c25 4.7u 1 2 3 4 5 10 9 8 7 6 sw3 fsi-dir sw3 fsi-dir r42 47k r42 47k c27 0.1u c27 0.1u + c28 1u + c28 1u r46 47k r46 47k r13 1k r13 1k r12 10k r12 10k r38 47k r38 47k + c23 10u + c23 10u flit 1 avss 2 pdn 3 smute 4 dem0 5 dem1 6 ilrck 7 ibick 8 sdti 9 idif0 10 idif1 11 idif2 12 cm0de0 13 cmode1 14 cmode2 15 odif0 16 odif1 17 sdto 18 obick 19 olrck 20 mclk 21 tvdd 22 dvss 23 vdd 24 u4 ak4121a u4 ak4121a 2 1 3 sw2 smute sw2 smute
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